Cisco C8510-SRP - Switch Route Processor Manuale Utente Scaricare il pdf (Pagina 9)

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Figure 6 Catalyst 8500 Switch Architecture

Catalyst 8500—Scalable System Architecture

The Catalyst 8500 is built from the ground up as a Cisco IOS

platform. It speciﬁcally enables Cisco IOS functions such as IP,

IPX, IP multicast, bridging, ATM switching and CiscoAssure

policy-enabled QoS in hardware ASICs.

The Catalyst 8500 switch router architecture is based on the

following key elements:

• Wire-speed, ﬂexible ASICs on the line cards that make the

packet forwarding and policy-based ﬂow classiﬁcation

decisions

• Nonblocking, low-latency, and rich QoS switching fabric for

advanced trafﬁc management

• MIPS architecture-based CPU running Cisco IOS software for

ensuring a stable network topology and fast convergence around

failures

• Flexible port interface modules that provide access to a wide

variety of media, including Ethernet, Fast Ethernet, Gigabit

Ethernet, and ATM and Packet over SONET (POS) in the future

Powerful CPU and ASICs for Scalable Control and

Forwarding

Integral to the Catalyst 8500 is the MIPS architecture-based CPU.

This CPU runs the Cisco IOS and routing protocols such as

EIGRP, OSPF, and PNNI, while also computing the Forwarding

Information Base (FIB). A highly optimized routing table lookup

algorithm, the FIB is a key technology innovation under the CEF

architecture. The FIB data structure is downloaded to the ASICs

on the line cards that make the packet-by-packet forwarding

(Layer 3 and Layer 2) decisions. The powerful CPU combined

with CEF’s separation of the data plane and the control plane

enables the network to converge quickly in the event of topology

changes, and minimizes the risk of packet loss. Additionally, the

CPU also handles system maintenance tasks such as running the

Cisco IOS CLI, environmental monitoring, retrieving packet

statistics, and so on.

In addition to making the forwarding decisions, the CEF

ASICs are also responsible for making policy-based ﬂow

classiﬁcations for QoS and ﬁltering. Flows are identiﬁed based on

IP precedence and type of service (ToS), providing a common

way to represent priorities on a network. Future enhancements

will include ﬂow identiﬁcation based on source IP address,

destination IP address, and TCP/User Datagram Protocol (UDP)

port combinations as well as Resource Reservation Protocol

(RSVP) signaling requests. The ASIC architecture is ﬂexible and

future proof. Each line card ASIC can be upgraded by performing

a simple microcode change that can be a part of the Cisco IOS

software image.

Flexible Port Interfaces

• GBIC Technology for GE, Fiber and Copper for FE(C), ATM and POS

• Nonblocking, low latency

• Dynamic buffering

with per-flow queuing

• Weighted Round Robin

(WRR) queuing and

scheduling for differentiated

delay and loss

• Traffic policing and

rate limiting

• Strict priority and rate

schedulers in MSR edition

• Runs routing protocols

(OSPF, EIGRP, PNNI, etc.)

• Computers forwarding

information base

• Hardware-based

packet switching and

route lookups

• Policy classification for

QoS and filtering

Distributed

FIB

Distributed

FIB

Routing

Table

Forwarding

Information

Base

Switch Fabric

Switch CPU

Line Module Line Module

FE GE

ATM

PoS

GEC

Rich QoS-Shared

Memory Fabric

Cisco IOS Route

Processor

Cisco Express

Forwarding ASICs

Cisco IOS Software

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